The present invention relates to integrated circuit (IC) system design and, more particularly, to identifying noise coupling among input/output (I/O) nodes of the components of the IC.
A System on a Chip (SoC) integrates, onto a single chip, several distinct functions, such as processing and memory that previously may have been implemented in distinct chips, such as a processor chip and a memory chip. A typical SoC includes a microprocessor module, a memory module, and one or more additional modules that may include, for example: timing sources such as oscillators or phase-locked-loop (PLL) circuits, interfaces, converters such as analog-to-digital (ADC) or digital-to-analog (DAC) converters, and power regulators. Some of these modules such as, for example, some PLLs and converters, use both digital and analog components and signals and are consequently referred to as mixed-signal modules. Digital components are generally clock-signal activated and include components such as logic gates and registers. Analog components are continuously active and include components such as capacitors and resistors.
Mixed-signal modules have input and/or output (I/O) nodes and may be particularly sensitive to noise coupling from the effects of switching activity by digital circuits on nearby analog circuits. Note that, as used herein, a module's I/O nodes include interfaces with any other module-external components, whether on-chip SoC components or off-chip components. A typical SoC includes a plurality of modules with densely laid out interconnections that interact in complex ways. This makes the SoC vulnerable to unintentional noise couplings and/or noise injections among the various modules' I/O nodes and lines. Reducing noise couplings would help make for more reliable SoCs.
Note that ICs may be said to comprise intellectual property (IP) blocks, which are also called IP cores. IP blocks refer to defined, designed, verified, and reusable IC building blocks. An IP block can refer to an entire module, such as, for example, a processor on an SoC, or to a portion of a module. IP blocks may be at any one of multiple levels of abstraction—similar to the way software blocks may be in pseudo code, source code, object code, executable code, or various other levels of abstraction. Correspondingly, IP blocks may be described as soft, firm, or hard. Soft IP blocks are typically in the form of netlists or hardware description language (HDL) files, and are fairly flexible in terms of physical implementation details. Hard IP blocks have predefined and detailed physical parameters for the components and are generally specific to a particular foundry. Firm IP blocks are in between hard IP and soft IP and have some predefined physical parameters, but are configurable to an extent.
It would be advantageous to be able to measure or test the mixed-signal modules of an SoC design for noise sensitivity due to cross-coupling.